The present invention relates to logic level translators, and, more particularly, to a logic level translator which comprises a TTL logic gate, a current switch, and a clamp circuit for converting CML level binary signals into TTL level binary signals.
Current data processing systems utilize transistor-transistor logic (TTL) and current-mode logic (CML) to manipulate, store, and process data which is represented in binary form. In many of the current data processing systems different types of logic may be used in different portions of the data processing system. In order to transfer data from one portion of the processing system to another portion of the processing system it is often necessary to translate from one type of logic signal into another type of logic signal.
Prior art signal translators use diodes and other semiconductor devices to obtain a fixed voltage drop in order to translate from one type of binary signal level to another type of binary signal level. These prior art signal translators use a common ground which is shared by both the input and the output signals. For example, a CML input signal and a TTL output signal would use the same bus line as a common ground. The TTL currents occurring in the common ground bus introduce noise signals in the CML portion of the translator. Also, variations in the power supply voltage used in the TTL portion are coupled to the CML portion of the circuit. Furthermore, TTL circuits generate self-induced noise at a level which is unacceptable when such is introduced into the CML circuits. Thus, it is important that the noise developed in the prior art translators be eliminated to prevent error signals from being generated in the output of the data processing system.
It is also a desirable feature of a logic level translator to prevent saturation in any of the switching transistors thereof in order to increase the operational speed of the translator.
According to one embodiment of the invention disclosed in U.S. Ser. No. 484,513 of D. L. Fett, filed July 1, 1974, and assigned to the same assignee as the present invention, a logic level translator is provided for converting TTL and DTL level binary signals into CML and ECL level binary signals. Such invention solves certain problems involved in the conversion of TTL level binary signals into CML level binary signals but does not concern itself with the above referred to problems and concerns involved in the conversion of CML level binary signals into TTL level binary signals.
It is therefore an object of the present invention to provide improved apparatus for translating CML level binary signals into TTL level binary signals.
Another object of the invention is to provide a logic level translator which substantially reduces the noise occurring in the CML and TTL portions of the translator.
A further object of the invention is to provide a logic level translator having a relatively high speed of operation in converting CML signals into TTL signals.
Yet another object of the invention is to provide a logic level translator in which the CML ground bus is isolated from the TTL ground bus.
These and other objects of the present invention are achieved by providing a logic level translator comprising a TTL logic gate, a CML current switch including differential current sources, and a clamp circuit. The current switch comprises a first transistor for switching current into the TTL logic gate in response to the CML signal input level and a second transistor for providing a quick pull-down on a portion of the TTL logic gate in order to reduce noise in the TTL circuit. The clamp circuit prevents the first transistor of the current switch from reaching saturation, thereby increasing the effective speed of the logic level translator. Separate grounds are provided for the TTL and CML portions of the translator.